This invention relates to data transmission method and apparatus suitable for transmitting binary data or multiple value data between plural active devices, to data processing apparatus for performing processing based on received plural data to obtain a result, and to a neural network which includes plural neuron devices.
With conventional computer systems, it is widely known that the ability of a computer system as a whole is improved by interconnecting plural processors to one another other than improving the ability of a single processor. In this computer system, when exclusive data transmission channels are used to interconnect each processor to other processors, the number of exclusive data transmission channels increases because plural processors should be interconnected to one another. As a result, the number of interconnectable processors is determined by a limitation of the number of exclusive data transmission channels physically possible to interconnect plural processors. On the other hand, when a data bus is used for transferring data which data bus is common to all processors, the disadvantage of being limited by the number of interconnectable processors is eliminated. Since the system must employ the bus arbitration interfaces for obtaining usage of the data bus for each processor, and must employ the protocols for indicating data sending processor and data receiving processor of data on the data bus, the data transmitting quantity is accordingly decreased. As a result, an ability is obtained which is fairly lower than theoristical ability expected by increasing the number of interconnected processors. When the computer system is required to transfer plural value data, the disadvantages described earlier are raised.
In a neural network, which has attracted wide attention in recent years, the disadvantages described earlier are raised distinctly. The neural network falls into two main groups; one group is a pattern association type, which corrects the weighting factor of the synapses by applying the input signal and teaching signal as a pair (refer to FIG. 21-A). Another group is an automatic association type which corrects the weighting factor of the synapses by applying only input signal (refer to FIG. 21-B).
More particularly, a neural network is intended to raise the speed of pattern recognition and characteristic abstraction and the like by using a device (hereinafter referred to as a neuron device) which realizes the function similar to the function of a nerve cell of a living thing. A neural network generally requires a remarkably large number of neuron devices.
FIG. 22 is a diagram schematically showing a nerve cell. Plural input signals are supplied to a sigma unit through synaptical couplings. An output from the sigma unit is applied to the threshold processing based on a sigmoid fuction, so as to output a signal as an input signal for other nerve cells. The sigma unit includes a terminal which is so called a threshold unit. The sigma unit is controlled by whether or not a signal is to be output therefrom based on level of a signal which is supplied to the threshold unit.
In the nerve cell, each input signal is given weight based on corresponding synaptical coupling, all input signals thus given weight being cumulatively added to obtain an added result. It is controlled by whether or not a signal is to be output from the sigma unit based on the added result and a threshold level. When the signal is to be output from the sigma unit, the signal is converted to a signal within a range of 0 to 1 based on the sigmoid function.
Because the synaptical couplings of a nerve cell are corrected to obtain an aimed result through repeating trial and error and studying processing, each neuron device within a neural network is accordingly required to have a similar function.
The pattern association type neural network requires an input layer, a medium layer and an output layer. Each layer consists of a required number of neuron devices which have an electrical construction equivalent to the schematic diagram of FIG. 22, and requires the electrical interconnection of all neuron devices between the different layers. Accordingly, the number of input signals of each neuron device belonging to the medium layer or the output layer is remarkably increased, but the number of input signal can be increased by only so many because of the physical restrictions of electrical interconnections. Consequently, a number of neuron devices have no practical use outside of research. For example, when pattern recognition of a figure data having 256.times.256 pixels is to be performed, a pattern association type neural network requires 256.times.256 neuron devices for an input layer. All neuron devices of the input layer are then interconnected to all neuron devices (a number of neuron devices is m, for example) of a medium layer, and all neuron devices of the medium layer are interconnected to all neuron devices (a number of neuron devices is n, for example) of an output layer. As a result, 256.times.256.times.m+m.times.n signal lines are required when exclusive signal lines are used, causing actual interconnection being impossible. On the other hand, bus arbitration interfaces become complicated following the increase in the number of neuron devices, and data transmission and cumulative addition are performed in a time sharing manner causing the working ratio decreased. Accordingly, the ability of the neural network as a whole is remarkably decreased. Also, the automatic association type neural network requires the interconnection to one another of all neuron devices which belong to a combination layer and interconnection of input synapses and all neuron devices. As a result, the disadvantages in the pattern association type neural network are greater when the number of neuron devices is the same as the number of neuron devices in the pattern association type neural network.
When input signals of a neuron device which is a part of a neural network are supposed as A, B, C, D and corresponding synaptical coupling (hereinafter referred to as weighting) are supposed as Wi1, wi2, wi3, wi4 (i is the number indicating the neuron device), AWi1, Bwi2, Cwi3, Dwi4 are supplied to the sigma unit .SIGMA. and cumulatively added. The cumulatively added result Xi (=AWi1+Bwi2+Cwi3+Dwi4) is converted to an intermediate value (multiple value data) within a range of 0 to 1 by a sigmoid function yi={1+e.sup.(-Xi+.theta.) }.sup.-1 and output therefrom. FIG. 22 also shows a threshold unit and an input data th which is supplied to the sigma unit .SIGMA. and is used for threshold processing. The weighting factors Wi1, wi2, wi3, wi4 are corrected by studying processing. In data transmission between neuron devices, not only binary signals but multiple value data should be output. Consequently, it is necessary to perform analog data transmission or multiple value data transmission instead of the binary data transmission widely employed in digital computer systems, causing the disadvantages above mentioned being increased. Furthermore, the sigma unit .SIGMA. is forced to accept a large number of input signals and to change the weighting factor for each input signal. Thus, the neuron device itself becomes complicated in its arrangement and becomes enlarged.
Disadvantages with respect to electric wiring similar to the above mentioned occur not only in neural networks and computer systems consisting of a large number of processors, but they also occur in a local area networks (hereinafter referred to as LAN) and the like.